1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to improvements in a circuit for reading data in a semiconductor memory device. More specifically, it relates to a configuration of a data read circuit for providing an assured optimal circuit operation even in the event of potential changes in a supply voltage.
2. Description of the Related Art
FIG. 1 illustrates a schematic configuration of an entire data read portion of a dynamic random access memory (DRAM) which is one of semiconductor memory devices. Referring to FIG. 1, the DRAM includes a memory cell array MA, an address buffer AB, an X decoder ADX, a Y decoder ADY, a sense amplifier and input/output circuit SI, and an output buffer circuit OB.
The memory cell array MA includes a plurality of memory cells arranged in matrix, each of which stores information.
The address buffer AB receives an external address signal A externally applied to generate an internal address signal a and applies the same to the X decoder ADX and Y decoder ADY. The address buffer AB receives a row address and a column address in a time division multiplexing manner.
The X decoder ADX receives the internal address signal a from the address buffer AB to generate a signal for selecting a corresponding row of the memory cell array MA.
The Y decoder ADY receives the internal address signal a from the address buffer AB to select a corresponding column or columns of the memory cell array MA. Timings that the X decoder ADX and Y decoder ADY receive the row address and the column address are, for example, provided by a RAS signal and a CAS signal, respectively. The signal RAS defines the timing that the X decoder receives a row address, while the signal CAS defines the timing that the Y decoder ADY accepts a column address.
The sense amplifier and input/output circuit SI is a circuit block including sense amplifiers and an input/output circuit. The sense amplifiers sense and amplify information stored in the selected memory cells of the memory cell array MA. The input/output circuit connects a corresponding column of the memory cell array MA to the output buffer circuit OB in response to a decoded address signal from the Y decoder ADY. That is, the input/output circuit SI outputs information of the selected memory cell or cells as read-out data D.sub.R to the output buffer OB in response to the decoded address signal from the Y decoder ADY.
The output buffer circuit OB is activated responsive to a clock signal .phi..sub.S and receives the read-out data D.sub.R to convert the data into corresponding external output data D.sub.OUT and output the same.
A control signal generator circuit CG is provided as a peripheral circuit for controlling various operation timings of the DRAM. The control signal generator circuit CG generates a precharge potential VB for precharging bit lines, a word line driving signal R.sub.n for driving a selected word lines, a sense up activating signal .phi..sub.S for activating the output buffer circuit OB, and sense amplifier activating signals .phi..sub.A and .phi..sub.B.
FIG. 2 shows a schematic configuration of the memory cell array MA in FIG. 1. Referring to FIG. 2, the memory cell array MA includes a plurality of bit line pairs BP0, BP1, . . . , BPm arranged in a column direction, and a plurality of word lines WL1, WL2, . . . , WLn arranged in a row direction intersecting with the bit line pairs BP0-BPm. A bit line pair BP (the BP is a general denotation for the bit line pairs BP0-BPm) includes complementary bit lines BL and BL. That is, the bit line pair BP0 includes a bit line BL0 and a complementary bit line BL0, and the bit line pair BP1 includes bit lines BL1 and BL1. Similarly, the bit line pair BPm includes bit lines BLm and BLm. This bit line pair BP provides a so-called "folded bit line scheme", and thus a single memory cell 1 is provided at respective intersections of each bit line pair BP and each word line WL.
The bit line pair BP is provided with a precharge/equalizing circuit 2 for equalizing and precharging to a predetermined potential VB potentials on the bit lines BL and BL of the bit line pair BP during a RAS precharge period (while the signal RAS is logical high or at the H level).
The bit line pair BP is further provided with a sense amplifier 50 for sensing and differentially amplifying a potential difference between the bit lines BL and BL. The sense amplifier 50 is activated responsive to the sense amplifier activating signals .phi..sub.A and .phi..sub.B. The sense amplifier 50 is supplied with two kinds of the activating signals .phi..sub.A and .phi..sub.B because the sense amplifier has normally such function as to discharge the potential on a lower potential bit line to a ground potential and boost the potential on the other higher potential bit line up to a supply voltage Vcc level, and thus it needs to be provided with timings to activate these charging and discharging operations.
Transfer gates T0 and T0', T1 and T1', . . . , Tm and Tm' are provided between the bit line pair BP and data input/output buses I/O and I/O, which selectively connect the bit lines responsive to the decoded address signal from the Y decoder ADY. The transfer gates T0 and T0' connect the bit lines BL0 and BL0 to the data input/output buses I/O and I/O, respectively, in response to an decoded address signal AD0. The transfer gates T1 and T1' connect the bit lines BL1 and BL1 to the data input/output buses I/O and I/O, respectively, in response to a decoded column address signal AD1. The transfer gates Tm and Tm' connect the bit lines BLm and BLm to the data input/output buses I/O and I/O, respectively, in response to a decoded column address signal ADm. An operation in data reading will now be described briefly.
First of all, the potentials on the bit lines BL and BL are precharged at a predetermined potential VB by the precharge/equalizing circuit 2. When a memory cycle is started, an external row address signal is accepted into an internal portion of the memory and transmitted to the X decoder ADX after the precharge was completed. The X decoder ADX decodes this internal row address signal to generate a signal for selecting a corresponding word line. Accordingly, the word line driving signal Rn is transmitted onto the selected word line, thereby raising the potential on this selected word line. As a result, in the case that the word line WL1 is selected, for example, memory cell data are transmitted on the bit lines BL, while the bit lines BL holds the precharge potential. The sense amplifiers 50 are then activated responsive to the activating signals .phi..sub.A and .phi..sub.B to sense and differentially amplify a potential difference on associated bit line pairs. After the potential difference on the bit line pair BP is established, a decoded column address signal is outputted from the Y decoder ADY to select one bit line pair, so that this selected bit line pair is connected to the data input/output buses I/O and I/O via the transfer gates. The data transmitted to the data input/output buses I/O and I/O is transmitted as read-out data D.sub.R to the output buffer circuit OB. The configuration of and operation of the output buffer circuit OB will now be described with reference to FIG. 3.
FIG. 3 only shows an output buffer circuit OB connected to a pair of the data input/output buses I/O and I/O. It should be noted that in a normal DRAM, the memory cell array MA is divided into a plurality of blocks. Therefore, the data input/output buses are provided corresponding to each of the divided blocks, and the output buffer circuit is provided corresponding to each pair of the data input/output buses.
Referring to FIG. 3, the output buffer circuit OB includes a current mirror type amplifier 3 for differentially amplifying a potential difference between the pair of data input/output buses I/O and I/O, and an output driver 4 for deriving output data D.sub.OUT responsive to an output of this current mirror type amplifier 3.
The current mirror type amplifier 3 includes n channel MOSFETs (insulated gate type field effect transistors) Q1, Q2 and Q5 and p channel MOSFETs Q3 and Q4. The n MOSFET Q1 has its gate connected to an internal data input/output line DL, its drain connected to a node N1 and its source connected to the drain of the n channel MOS transistor Q5. The n channel MOSFET Q2 has its gate connected to an internal data input/output line DL, its drain connected to a node N2 and its source connected to the drain of the n channel MOSFET Q5. The p channel MOSFET Q3 has its source connected to a first supply potential Vcc, its gate connected to the node N2 and its drain connected to the node N1. The p channel MOSFET Q4 has its gate and drain connected to the node N2 and its source connected to the first supply potential Vcc. The n channel MOSFET Q5 has its gate connected to receive the sense up activating signal .phi..sub.S, its drain connected to the respective sources of the n channel MOSFETs Q1 and Q2, and its source coupled to a second supply potential (the ground potential).
The p channel MOSFETs Q3 and Q4 form a current mirror circuit and also function as loads for the n channel MOSFETs Q1 and Q2. The n channel MOSFET Q5 activates this current mirror type amplifier 3 responsive to the sense up activating signal .phi..sub.S and also functions to keep constant a current flowing therethrough.
Data being complementary with each other are outputted from the nodes N1 and N2 to be sent to the output driver 4.
Diode-connected n channel MOS transistors Q6 and Q7 are provided to bias the potentials on the data input/output buses I/O and I/O, i.e., the internal data input/output lines DL and DL to a predetermined potential. The n channel MOSFET Q6 has its gate and drain connected to the first supply potential Vcc, and its source connected to the data input/output bus I/O. The n channel MOSFET Q7 has its gate and drain connected to the first supply potential Vcc and its source connected to the data input/output bus I/O. These diode-connected MOSFETs Q6 and Q7 bias the data input/output buses I/O and I/O to the potential of (Vcc-V.sub.TN), respectively. The V.sub.TN presents threshold voltages of the n channel MOSFETs. An operation of the output buffer circuit OB will now briefly be described.
As has been described, the data of the selected memory cell is transmitted onto the data input/output buses I/O and I/O by the Y decoder ADY. Accordingly, the potential on one of the data input/output buses I/O and I/O charged to the potential (Vcc-V.sub.TN) is lowered, which is connected to the bit line of logical low or the L level. Meanwhile, the potential on the other data input/output bus connected to the bit line of the H level is not lowered but maintained at the potential of (Vcc-V.sub.TN). This is possible because a parasitic capacitance of the data input/output buses I/O and I/O is fairly larger than that of the bit lines BL, thereby less causing a rise in potential.
The potential difference occurring between the data input/output buses I/O and I/O is amplified by activating the current mirror type amplifier circuit 3 in response to the sense up activating signal .phi..sub.S. The amplified data is transmitted to the output driver 4 to be converted into an external data Dout therein and outputted to the outside of the device.
The current mirror type amplifier circuit 3 including the differential MOSFETs Q1 and Q2 at its input portion has its sensitivity usually influenced by the levels of bias potentials applied to its input terminals (the gates of the MOSFETs Q1 and Q2). That is, when the bias voltages applied to the input terminals of the amplifier circuit 3 are raised above a certain voltage level, a voltage to be applied to the drain of the constant current MOSFET Q5 is raised responsively. It should be noted here that the MOSFETs Q1 and Q2 are ON due to the bias voltages of the data input/output buses I/O and I/O In the case that the amplifier circuit 3 operates at a voltage such as of +5V, the constant current MOSFET Q5 does not provide an ideal constant current characteristic because its drain voltage is limited to a comparatively low value. Therefore, the drain current of the constant current MOSFET Q5 is increased by raising its drain voltage. The increase in the drain current of the constant current MOSFET Q5 increases the drain currents of the MOSFETs Q1 and Q2 at the input portion of the amplifier circuit 3. In this case, when the potential on the complementary data input/output bus I/O (i.e., the internal data input/output line DL) becomes lower than that on the internal data input/output bus I/O (i.e., the data input/output line DL) in accordance with the read-out data, the drain current of the MOSFET Q1 is increased, while that of the MOSFET Q2 is decreased. As a result, the potential on the node N1 is lowered, so that a voltage signal of the L level is transmitted from the node N1 to the output driver 4.
In contrast, when the potential on the data input/output bus I/O becomes lower than that on the complementary data input/output bus I/O the drain current of the MOSFET Q1 is decreased, while that of the MOSFET Q2 is increased. As a result, a signal of the H level is outputted from the node N1. In this case, however, a drain voltage of the MOSFET Q2 is lowered by a voltage developing across the source and drain of the p channel MOSFET Q4. Therefore, the increase in the drain current of the MOSFET Q2 is comparatively small. The potential on the node N2 is fed back to the gate of the p channel MOSFET Q3. Thus, the increase in a voltage to be applied across the gate and source of the MOSFET Q3 is limited to a comparatively small value. Accordingly, the increase in the drain current of the MOSFET Q3 becomes comparatively small. Despite the fact that the drain current of the MOSFET Q1 is increased by the increase in the drain current of the constant current MOSFET Q5, the increase in the drain current of the MOSFET Q3 is comparatively small, so that the high level signal to be outputted from the node N1 attains a comparatively low level.
In the case that a gain of the amplifier circuit 3 is increased by making drain-source conductances of the MOSFETs Q3 and Q4 comparatively small, the level of the high level signal is lowered remarkably as the bias voltage to be applied to the pair of input terminals is raised. This level lowering of the high level signal from the amplifier circuit 3 prevents the output driver 4 from performing an accurate data deriving operation.
When the bias voltage to be applied to the input terminal pair of the amplifier circuit 3 is lowered below a certain value, the drain current of the constant current MOSFET Q5 is decreased. This decrease in the drain current of the constant current MOSFET Q5 causes a decrease in a charging current to be supplied to an input capacitance of the output driver 4 via the MOSFET Q3 or a decrease in a discharging current to be supplied to the input capacitance of the output driver 4 via the MOSFET Q1, thereby reducing the operation speed of the amplifier circuit 3.
Bias potentials on the data input/output buses I/O and I/O are lowered to appropriate levels by the MOSFETs Q6 and Q7. That is, respective potentials on the data input/output buses I/O and I/O are set to the appropriate level (Vcc-V.sub.TN) by the MOSFETs Q6 and Q7 in order to improve the operation speed and the sensitivity of the amplifier circuit 3 and perform an accurate data reading operation.
It is empirically known and disclosed, for example, in U.S. Pat. No. 4,507,759 that the amplifier circuit 3 has its sensitivity enhanced by biasing respective potentials on the data input/output buses I/O and I/O to the level (Vcc-V.sub.TN) and thus operates in an optimal state.
In general, it is desired for an integrated circuit to be assured of performing an accurate circuit operation even with a fluctuation of the supply voltage. Therefore, the circuit need be designed so as to perform the circuit operation in the optimal state even if the supply voltage Vcc fluctuates in the range of approximately .+-.10%. A description will now be given on an operation of the amplifier circuit 3 in the fluctuation of the supply voltage.
FIG. 4 schematically shows the fluctuation in the potential V.sub.IO of the data input/output buses I/O and I/O (hereinafter referred to as "input/output potential V.sub.IO ") in accordance with the fluctuation of the supply voltage Vcc.
As shown in FIG. 4, Vcc 1 indicates a normal supply potential, and Vcc 2 indicates a potential rise by .DELTA.V above the normal supply potential Vcc 1.
The supply voltage Vcc is at the level of the Vcc 1 during the time period t0-t1. In this state, the diode-connected n channel MOSFETs Q6 and Q7 are both ON, and therefore the input/output potential V.sub.IO is set to a desired potential (Vcc 1-V.sub.TN).
It is now assumed that the supply voltage Vcc is raised by .DELTA.V toward the potential Vcc 2 for some causes from the time t1 to the time t2. The MOSFETs Q6 and Q7 are both ON also during this period, so that the input/output potential V.sub.IO also rises as the supply voltage Vcc rises. The potential V.sub.IO of the data input/output buses I/O and I/O is finally set to the level of (Vcc 2-V.sub.TN).
The MOSFETs Q6 and Q7 are both ON during the period from the time t2 to the time t3 when the supply voltage Vcc is kept at the potential Vcc 2, so that the input/output potential V.sub.IO is also set to the potential of the (Vcc 2-V.sub.TN).
The raised supply voltage Vcc is lowered from the vcc 2 to the Vcc 1 during the period from the time t3 to the time t4 after the time .DELTA.t1 has elapsed. In this case, the potential on the data input/output buses I/O and I/O is at the (Vcc 2-V.sub.TN), so that the diode-connected MOSFETs Q6 and Q7 are turned off because their anodes are on the side of the supply voltage Vcc. As a result, a current does not flow from the data input/output buses I/O and I/O to a power supply Vcc, and thus the input/output potential V.sub.IO is not lowered in accordance with the lowering of the potential of the supply voltage Vcc.
Consequently, the input/output potential V.sub.IO is gradually discharged through the MOSFETs Q6 and Q7 or a "leak resistance" (a reverse resistance at an PN junction) being parasitic to the data input/output buses I/O and I/O. Accordingly, the input/output potential V.sub.IO is slowly lowered to reach the potential (Vcc 1-V.sub.TN) at the time t5 delayed by .DELTA.t2 from the time t4. This time period .DELTA.t2 is, for example, several hundreds mili seconds to several seconds long, which is not a negligible length for the circuit operation.
As described above, in the case that the supply voltage Vcc is once raised above the normal supply potential Vcc 1 and again recovered to the potential Vcc 1, the recovery of the input/output potential V.sub.IO is considerably delayed. As a result, the input/output potential V.sub.IO is set higher than the potential (Vcc-V.sub.TN) during the period from the time t3 to the time t5, thereby degrading the amplifiability and sensitivity of the current mirror type amplifier circuit 3, and thus optimal operations of the output circuit OB such as the optimal operation speed and detecting sensitivity are not guaranteed.
Such configuration is disclosed in the aforementioned U.S. Pat. No. 4,507,759 by Yasui et al that a common data line potential is biased to the potential (Vcc-V.sub.TN) in a static memory, and also a higher resistance for holding this bias potential is provided on the common data line. However, the prior art reference only discloses therein a configuration that the common data line is biased to a predetermined potential only in operation of the current mirror type amplifier circuit, and hence the reference is not directed to a problem concerning a potential fluctuation of the common data line which is accompanied by the fluctuation in the supply voltage.
Such configuration is disclosed in the U.S. Pat. No. 4,670,706 by Tobita that a p channel MOS transistor is provided between an output terminal and ground to make an output voltage of a voltage generating circuit stable. In this prior art, the voltage generating circuit has p channel and n channel MOSFETs connected complementarily with each other at an output stage, and thus a noise voltage is removed and also power consumption is reduced by operating these MOSFETs at the output stage at a critical state between a conductive state and a non-conductive state.